Generally, a volatile semiconductor memory device such as a DRAM has been developed to a high-speed and high-integrated memory in order to mate with the high performance of an electronic system such as a personal computer or an electronic communication apparatus. In addition, since a low power consumption characteristic is important in the case of a mobile DRAM used for a cellular phone or a notebook computer, research and development have been actively performed to reduce operational current and stand-by current.
The data retention characteristic of a DRAM memory cell including a transistor and a storage capacitor is very sensitive to the temperature. Accordingly, the semiconductor memory device is adaptively controlled according to temperature characteristics, thereby greatly reducing power consumption. For example, there has been proposed a method of adjusting a refresh period based on temperature information detected by a thermal sensor installed in the semiconductor memory.
FIG. 1 is a view showing the structure of a typical mobile DRAM.
As shown in FIG. 1, the typical mobile DRAM includes an input pad unit 1 equipped with a thermal sensor 10, a thermal code transmission circuit 12, and a TQ pad 14, a peri-area 2 formed with a global metal line 20, and a data pad unit 3 formed with a plurality of DQ pads 30.
The thermal sensor 10 generates thermal codes T0 to T5 including internal thermal information of the mobile DRAM and a high-temperature determination signal TQ85 enabled when the internal temperature of the mobile DRAM is 85□ or more. The high-temperature determination signal TQ85 is output through the TQ pad 14. The thermal code transmission circuit 12 receives the thermal codes T0 to T5 to generate output thermal codes T<0:5>, and the output thermal codes T<0:5> are output through a plurality of DQ pads 30 using the global metal line 20.
Generally, the thermal sensor is mounted on the input pad unit 1 having a spatial margin in the mobile DRAM. Accordingly, in order to output the thermal codes T0 to T5 generated from the thermal sensor 10 to the DQ pad 30, the output thermal codes T<0:5> must be delivered to the DQ pad 30 through the global metal line 20 formed in the peri-area 2. Since the global metal line 20 occupying an area of 8×8000 μm is typically required to transmit 6-bit output thermal codes T<0:5>, the global metal line 20 exerts a serious influence on the size of the mobile DRAM chip. In addition, since the output thermal codes T<0:5> must be delivered by using the global metal line 20 passing through the peri-area 2, the output driver must be enlarged.